Thermofluidic chip containing virtual thermal wells

Thermofluidic chip containing virtual thermal wells


The authors describe a thermofluidic chip on which microscale islands of controlled temperature are formed within an open fluidic environment. The chip forms part of the authors’ technology for thermally controlled DNA synthesis, whereby the site-specific temperature control enables site-specific addressability of chemical reactions, for example, related to the phosphoramidite cycle. Here, the authors discuss the principle of the chip, supporting the thermal well concept by means of simulations as well as by showing a prototype thermal array device.

1 Introduction

As exemplified by the thermal control of oligonucleotide melting and hybridisation within the polymerase chain reaction (PCR) cycle, the control of temperature plays an important role for DNA biochemistry. Usually, thermal cycling is performed with the biochemical species localised into a closed fluidic environment such as a 96-well microtitre plate. However, there are examples of multiple thermal regions within a microfluidic system, particularly in the context of miniaturised PCR reactors [1] but also for DNA hybridisation studies [23]. Here, motivated by the ability to control a very large number of DNA synthesis reactions in parallel, we use silicon microelectromechanical systems (MEMs) manufacturing technology to engineer a scalable microfluidic thermal array, each array element having the potential for distinct and controllable temperature.

By setting the temperature of the sites within the Evonetix microfluidic thermal array, we gain control, at each site within the array, over the rates of chemical reactions used for oligonucleotide synthesis. This approach is applicable to a thermally optimised phosphoramidite cycle [4] as well as to emerging enzymatic approaches to synthesis [5]. Using local thermal control, reactions within a global fluidic environment can be enhanced at hot sites with respect to cold sites and, after optimisation for thermal selectivity, the reactions can be considered ‘enabled’ or ‘disabled’ at each site. In this way, an array of heterogeneous oligonucleotides can be synthesised in parallel, without the onerous requirement that each site experiences a distinct sequence of reagents.

2 Requirements of a thermal array

We begin by considering the general requirements of a thermal array, first noting that the array should be manufacturable using standard semiconductor processing to achieve a high yield, allow the integration of electronics, and to enable features with micrometre dimensions.

To ensure acceptable total power requirements, each individual heater should have a high thermal resistance – the temperature rise per unit of electrical power dissipated. The task of fabricating Si-based electrical devices with high thermal resistance (RT> K/mW) is encountered, for example, during the development of bolometers [6], flowmeters [78], micro-hotplate gas sensors [914], and in biochemical chips [13]. An electrical device fabricated on silicon intrinsically has a low thermal resistance for the reason that silicon is an excellent thermal conductor (thermal conductivity, κ = 130 W/m K). While SiO2, another commonly available material within semiconductor manufacturing, has a lower thermal conductivity than Si by two orders of magnitude (κSiO2 = 1.3 W/m K), it may still not be sufficiently low to achieve the required thermal resistance when used as a solid support. To this end, geometry can be used to increase the thermal resistance – a common approach being to support the electrical device on an SiO2 membrane with a thickness in the micrometre range [812]. Alternatively, a fraction of the SiO2 material underneath the electrical device can be removed, replacing the removed material with air (κair = 0.025 W/m K) [1516].

The electrical power dissipated as heat at each thermal site must find a sink. If the whole supporting die were to have a high thermal resistance, then the power dissipated at each site would end up leading to an overall temperature rise of the fluidic environment. This in turn would lead to unwanted thermal cross-talk between thermal array elements. So, there must be a local heat-sink surrounding each thermal site. In this case, the high thermal conductivity of silicon is advantageous, and the heat-sink can be provided by surrounding each site by crystalline silicon.

Other thermal requirements include the means to dissipate electrical power, one option being metal (e.g. Pt, W) tracks fabricated on the substrate; alternatively, it is possible to use Si tracks or even active Si devices such as transistors. It must be possible to measure temperature at each site and this is achievable, for example, using the change in electrical resistance of the metal heater tracks with temperature: the electrical resistance of bulk Pt is known to increase at 0.385%/K. Also, since there will be a specification for temperature to be constant on the site within some range, the heater tracks need to be designed, so that there is more power per unit area dissipated around the perimeter of the heater than in the centre. Likely, patterning the heater tracks alone will not achieve a uniform temperature, so a heat-spreading material made from a highly thermally conducting material needs to be included either above or below the heater itself. The design of both heater and heat spreader require simulation of the heat diffusion equation.

Several requirements drive the size of each thermal element, including the surface area required for bio-functionalisation, the die size available together with the number of sites required in the array, and the heat-sink area required between thermal sites. Depending on the specific requirements, the thermal site is likely to take dimensions in the range 10 μm–1 mm.

3 Thermal simulations illustrating the thermal well concept

We perform thermal simulations based on the conduction of heat and confirm that a silicon-based substrate can provide a suitable platform for a thermal array. The thermal simulations are performed in two dimensions (2D) and consist of finding the steady-state temperature for a domain that consists of spatially varying thermal conductivity and localised heat sources. The perimeter of the simulation is held at constant temperature.

In the simulation, we consider a substrate which consists of alternating regions with length 200 μm which are either filled with silicon or partially filled with SiO2 (Fig. 1a). As previously described, several strategies towards thermal isolation are possible. The approach with regions of an Si wafer partially filled with SiO2 is attractive since it combines good thermal isolation with high mechanical strength [1516]. The surface of the substrate is covered with SiO2 and over the heater, there is an Au heat spreader. Underneath the heat spreader is a heater. Above the planar surface of the chip lies a layer of fluid, covered by an SiO2 flow-cell lid.


Thermal simulations, in two dimensions, of the heater chip covered both by water and a glass flow cell lid

(a) Thermal conductivities used in the simulation. They contain a 50 μm high section of the chip with regions of Si and a 20% fill-factor of SiO2, and a 4 μm thick SiO2 membrane with localised regions of 2 μm thick gold. The surface of the chip is covered with 30 μm of water topped with 40 μm of the enclosing flow-cell lid,

(b) The power densities used for the heater tracks. Each heater contains five tracks with the power dissipation at each track increasing with distance away from the centre of the heater,

(c) The resulting steady temperature distribution. The white lines indicate the extent of the fluid,

(d) Temperature profile at the surface of the heat spreader

Two thermal sites driven at different powers are considered in the simulation. The left site is set at a power/unit length of 170 W/m and the right site is at 85 W/m. The steady-state temperature rise (Fig. 1c) shows the resulting virtual thermals wells and, on examining a cross-section taken at the surface of the Au heat spreader, it is possible to see that excellent uniformity of temperature (<1 K) is achieved. This is both because of the heat spreader and since the outermost heater tracks are chosen to dissipate more power than the inner ones. The higher temperature heater achieves a 62 K temperature rise, and if a 100 μm heater length were to be considered then 17 mW of power is needed, giving a thermal resistance of 3.7 K/mW.

The virtual wells are also robust to relatively high flow velocities. This is readily seen by simulation (Fig. 2), adding a parabolic flow profile into the previous steady-state thermal simulation. There is little change to the temperature profile at 0.1 and 1 mm/s and a large, in the case of microfluidics, peak velocity of 10 mm/s is required to produce a measurable change in the temperature profile. Physically, the reason that the temperature profile is insensitive to flow-rate is that the heat-flux by fluid flow at these velocities is small when compared with the heat-flux by conduction.


Simulations of the temperature profile at the surface of the heat spreader in the case of a parabolic flow profile, within the 30 μm height channel, with peak flow velocities of

(a) 0.1 mm/s,

(b) 1 mm/s,

(c) 10 mm/s

The simulations illustrate that, by suitable engineering of a silicon substrate, it is possible to create virtual thermal wells within an open fluidic environment. Also, considering the surface of the Au heat spreader to be chemically functionalised, it would be possible to maintain a precise temperature for chemical reactions at that surface even under the flow of reagents.

4 Prototype thermal array devices

We describe a device structure capable of providing the thermal conductivities employed in the simulation. Looking at a plan view (Fig. 3a), a Pt heater is shown to sit on an SiO2 platform surrounded by Si. The SiO2 platform consists of a membrane supported by pillars and a cross-section (Fig. 3b) shows how the 20% fill-factor of SiO2 is achieved by 50 μm high pillars which extend from the substrate surface to a buried oxide layer.


Schematics and micrographs of the thermofluidic chip

(a) Plan view of the heater unit cell, showing the Pt heater supported on a thermally isolated SiO2 platform processed from an Si substrate (Si3N4 not shown),

(b) Cross-section (not to scale) through the heater unit cell showing the SiO2 membrane supported by SiO2 pillars. The membrane thickness is 5 μm, consisting of SiO2 (4 μm) and Si3N4 (1 μm) films,

(c) Micrograph of the 3 × 3 heater array together with a zoom-in (d) of the individual heaters showing the Pt heater traces, the through silicon vias (TSVs) that connect the heaters to a passive back-plane, and the SiO2 pillars. In both micrographs, the scale bar (solid line) corresponds to 100 μm

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